Run though the program timing is not nervous, also will be a problem, but recently in the optimization program, eliminate the warning program, found in the program to use division places called the similar warnings, as shown in figure molecules is a 16-bit wide, integrated SLACK after negative

Guess for a CLK clock division enough to get the final result, as a result of the delay output, but my program timing is not nervous, it doesn't matter even if such a cycle, so, there is no problem to use, consult bosses, how to restrain the divider causes problems, or constraint driven the clock?