In the test signal integrity between FPGA and phy, found the eye diagram quality has a problem, the graphics below

Test method, the diagram below, already very close to the receiver, and the fpga internal to the euro 100 matches

Really don't know the problem is how to produce, please great god guidance!

CodePudding user response:

Regulation under the FPGA driver ability, the current is how many?

CodePudding user response:

Hello, have tried to add the internal pull-up, but no effect

reference 1st floor CL3_14 response:

adjust the driving ability of the FPGA, the current is how many?

CodePudding user response:

Can you upload the that piece of circuit?

CodePudding user response:

Thank you for your help, probably drew a sketch

The

reference 3 floor CL3_14 response:

can you upload your that piece of circuit?

CodePudding user response:

Add that the phy and go line between fpga is according to 50 ohms, capacitance are close to the receiver

stitch reference 4 floor war Pikachu response:

thank you for your help, drew a sketch about

Quote: refer to the third floor CL3_14 response:

Can you upload the that piece of circuit?

CodePudding user response:

What type of PHY, PHY chip has a Radj swing adjustable resistance, can have a try,
See you this diagram, can be understood as two MB PHY docking?

CodePudding user response:

1) PHY AR8033, tried to adjust the output voltage peak to peak, in addition to the eyes a bit higher, other nothing changes,
2) we tried the output of the phy and fpga disconnected, and add a termination resistors, measured the eye diagram of good quality (below), but in the fpga becomes poor, so do not think with output

3) again to do a test: will the fpga signal output difference to their own the other pair of difference in charge of the foot, external and euro 100, measured as follows, the effect of rising edge not drab, eye diagram node

refer to 6th floor CL3_14 response:

what type of PHY, PHY chip has a Radj swing adjustable resistance, can have a try,
See you this diagram, can be understood as two MB PHY docking?

CodePudding user response:

1. The problem of PHY chip driver ability,
2. Set up inside the FPGA difference, bias resistors set is too small (ohms), cause the FPGA ate too much current, can check the FPGA bias resistors is set over there?